Graphic display system

ABSTRACT

Graphic display system for graphically indicating the responses from a number of students to a question wherein the sampling cycle for displaying the answers to each question is based on the time that a certain percentage of the students take to answer that question.

United btates Patent 1191 1111 3,818,483 Yamauchi et al. June 18, 1974GRAPHIC DiSPLAY SYSTEM 3,190.014 6/1965 Rhodes 35/48 R 1151 SawshiYamauchi, Tokyo; Takashi 33113335? 251323 l?!1;;;;3;;11111i1...........11111 31273315 Asaka, both of Japan 3,500,1153/1970 Augcr 340 324 A x A. 3,501,676 3/1970 Adler et al. 340/324 M X[73] Asslgnee' 3,548,806 12/1970 Fisher 346/37X [22] Filed: Oct. 3, 1972[21] Appl. No.: 294,636 Primary Examiner-David L. Trafton Attorney,Agent, or FirmC0oper, Dunham, Clark, [30] Foreign Application PriorityData Gnffin & Moran Oct. 4, 1971 Japan 46-77648 52 us. c1..........340/324 R, 35/48 R, 235/92 EA, [57] ABSTRACT 5 I Cl Graphic displaysystem for graphically indicating the D responses from a number ofstudents to a question [5 l d 0 32? g 5 wherein the sampling cycle fordisplaying the answers /3 3 l5 5/4 to each question is based on the timethat a certain References Cited Egrfcenta/ge of the students take toanswer that ques- UNITED STATES PATENTS 2,933,648 4/1960 Bentley 340/324M x 7 Bi n 8pr awin Figures PATENTEB JUN 1 81974 SHEU 6 BF 7 mm o 4m 07w 01 mm;

GRAPHIC DISPLAY SYSTEM BACKGROUND OF THE INVENTION The present inventionrelates to the graphic display system and more in particular, thepresent invention relates to the graphic display adopted for indicatingdynamic phenomenon.

The so called teaching machine for giving questions to a large number ofstudents and for finding the total of the answers from the students, isgenerally known to those skilled in the art. In the conventionalteaching machine, the periodically changing answering phenomena ofstudents to a certain question, are recorded in penrecorder in mostcases. The above mentioned penrecorder system is adopted for carryingout the analysis and analytical research of the answering phenomenathereafter, but it is not adopted for instantaneously observing theperiodically changing answering phenomena.

In order to overcome the above mentioned drawback of the conventionalpenrecorder system, those skilled in the art can easily think of theemployment of graphic display for graphically indicating various kindsof phenomena electro-optically, in place of penrecorder. However, inaccordance with the conventional display devices, the following problemsare brought about because the sampling cycle, i.e., the timecorresponding to the unit scale width in the direction of time axis onthe indication surface. For example, when a certain question is given tostudents, the time required for the answers of the students to thequestion, is greatly varied by the ease or difficulty of the question orthe abilities of the students. Therefore, when all the answeringphenomena ranging from the case where the answering time is short, tothe case where the answering time is long, are to be displayed on thesame display indication surface, it is necessary to extend the time axison the indication surface, and the size of the display device isexcessively increased. On the contrary, when the time axis on thedisplay surface is made short, it is impossible to sufficiently indicatethe answers in the case of a question that takes a long time to answer.

The object of this invention is to provide a graphic display systemwhich overcomes the above mentioned problems of the conventionaldevices.

Another object of the present invention is to provide a graphic displaysystem capable of automatically changing the sampling cycle inaccordance with the change of the speed with which the questions areanswered.

In accordance with an embodiment of the present invention, when acertain question is given to a number of students, the time rate of theanswers of the students to the question can be graphically indicated onthe indication surface by luminescent diodes, discharge tubes on a CRT.First, the time (1') required from the presentation of a question to theresponse of, for instance, 5 percent of the students, is measured. Next,the repetitive cycle of the sampling pulse for displaying the answers isdetermined on the basis of the time (1'), and thereafter, the studentanswers are displayed on the indication surface. At the same time, thescale in the direction of time axis on the indication surface isdetermined on the basis of said time (1').

The details of the present invention are explained in accordance withthe attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the rateat which the students provide answers to a typical question;

FIG. 2 is a block diagram showing a sampling pulse generating circuit asthe main portion of the graphic display device of the present invention;

FIG. 3 is a diagram showing the circuit of a display panel utilizing anumber of discharge tubes;

FIG. 4 is a diagram showing the circuit of a display panel utilizing aplural number of luminescent diodes;

FIGS. 5A and 5B, when fitted together as shown in FIG. 5, are a blockdiagram showing an embodiment of this invention utilizing theluminescent diode display panel;

FIGS. 6A and 6B, when fitted together as shown in FIG. 6, are a blockdiagram showing another embodiment of this invention utilizing a CRT.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows the diagram showinghow the rate of response from the students to a typical question. InFIG. 1, .the abscissa shows time, and the ordinate indicatesanswer-rate.

What is meant by answer-rate in this specification is defined by thefollowing formula;

FORMULA Answer-rate Number of students who have answered/Total number ofstudents X 1) From FIG. 1, it is seen that the answer rate of thestudents is extremely low till a certain period of time has passed fromthe time when the question is given to the students (the time is shownby -r) and when the time T has passed, it is a logarithmical curve. And,for example, when the 31' time has passed, the answer rate arrives atcertain level. The time T is greatly varied by the ease or difficulty ofthe question, or by the ability of students. In the same manner, thegradient of the curve after having passed the time T is closely relatedto the time 1'. In other words, when the time 1 is large, the gradientof the curve becomes dull," and when the time 1' is small, the gradientbecomes sharp.

Therefore, in accordance with the present invention, the time till theanswer rate becomes such as 5 percent is measured, this time is definedas the time 1, and from the time 1', the time, i.e., the sampling cycleof the display curve is determined. In other words, the unit time (t)showing one unit of the time axis of the display is changed incorrespondence to the time (T). Therefore, in accordance with thepresent invention, it becomes possible to accurately and convenientlyindicate the student answers on the same display surface even when theanswer time varies greatly from question to question the answer time.

In the following paragraphs, the method for generating the samplingpulse, which is the essence of the present invention, is explained inaccordance with FIG. 2.

In FIG. 2, A-Counter l is a binary counter for counting a first pulsetrain P,, and B-Counter 2 is also a binary counter for counting a secondpulse train P A start signal P, changes to a high level at the time whena question is given to the students. On the other hand,

a stop signal P, changes to a high level when the rate of the answer tothe question reaches percent. The stop signal P, may be provided, forexample, by a counter 2a which receives as an input answer responsesover a line l and provides and output when its count reaches apredetermined number corresponding to 5 percent of all answerers.Namely, the time ranging from the time when the start signal P, hasbecome high, to the time when the stop signal P, becomes high,corresponds to the time (1'). When the start signal P, becomes high aflipflop F, takes its set state, and the set output of flipflop F, issupplied to an AND Gate 0,. Therefore, when the flipflop F is set, thefirst pulse train P, passes through the AND Gate G, and is supplied toA-Counter l, and is counted. Thereafter, the student answers start andare suitably counted, and when the answer-rate reaches 5 percent, theflipflop F, is reset by the stop signal P,. Thereby the countingoperation of A-Counter 1 stops. In this case, a value corresponding tothe time (7) till the answer rate has reached 5 percent is set in A-Counter l.

The reset output of flipflop F, is supplied to the AND Gate 6' andtherefore when the flipflop F, is reset, the second pulse train P passesthrough the AND Gate G, and is supplied to B-Counter 2 to be counted.

When the count in B-Counter 2 agrees with the contents of A-Counter l, acoincidence output is emitted from a coincidence circuit 3, to drive amono-multivibrator 4. P, is the output pulse from themono-multivibrator-4. B-Counter 2 is cleared by this pulse P,, andthereafter, when pulse P, is eliminated, B-Counter 2 starts countingagain, and the content thereof is compared with the content of A-Counterl. Thereafter, the above mentioned operation is repeated, and the pulseP, having the predetermined repetitive cycle is emitted from themono-multi-vibrator 4.

Suppose that the repetitive cycles (the periods) of the first pulsetrain P, and the second pulse train P are respectively set to be T, and7 and that the two repetitive cycles are interrelated by the below givenformula;

FORMULA:

T, n'T

When the counting of A-Counter l is set to be n,, the

time (T) is obtained by the following formula; FORMULA:

When the formula (2) is substituted in the formula (3), the followingformula can be obtained; FORMULA:

1' n,'n'T,,

On the other hand, when the counting of B-Counter 2 is supposed to be nthe cycle T, of the pulse P, can

be obtained by the following formula; FORMULA:

Therefore, from the formulae (4) and (5), the below given formula (6)can be obtained; FORMULA:

r mln n'T,

When the contents of the two counters 1 and 2 coincide, r1, becomesequal to 21:, and therefore, the formula (6) becomes as follows;

FORMULA:

From the above given formula (7), when it is presumed that onegraduation of the display surface time axis corresponds to the pulse P,,the time T is always represented by the (n) number of graduations. Inother words, the repetitive cycle (Le. the period) of the pulse P, ischanged in correspondence to the way the time (1) changes. lo thepresent invention, the pulse P, is utilized as the sampling pulse. Thecycle T, represents the fineness of the divisions of the unit time I,and is the factor for determining the precision of the cycle T,., andtherefore. it is preferable that T, is smaller. On the other hand, theinteger :1 stands for the number of the graduations dividing the time(1-), and determines the fineness of the reproduced graph, and thereforeit is better when the value of n is greater. When the grad uations aredetermined as mentioned above, the counting (n) ofA-Counter l isindicated on the position of graduations corresponding to the time (T)on the time axis of the indication surface, and the values of 2:1 or 3nare indicated on the graduations corresponding to 21 and 37.

FlG. 3 is a diagram showing an embodiment of the graphic display panelin which indicating discharge tubes are used.

As shown in FIG. 3, X drive lines X,-X,, are extended from the stagesofa counter 6, which is an X drive circuit and Y drive lines Y,-Y,,, areextended through transistors TR -T mm hich are an Y drive circuit 7. Adecoder Sis connected with the Y drive circuit 7. Indicating lampsL,,-L,,,,, are disposed at the points of intersection between the X andY drive lines and the voltages V, and V, are applied to the terminals ofthe indicating lamps L,,-L,,,,, through resistors.

The answer indicating data arrives on the input lines I. The number ofanswers generally increases as time elapses and converges toward acertain value after a predetermined time. A low-level signal appears onthe Y drive line of the stage which corresponds to the decode output ofthe decoder 5. in response to the timming pulses P, illustrated in FlG.2 a time axis counter in the x-drive circuit 6 steps so that low-levelsignals appear on the X drive lines sequentially. As a result theindicating lamps l. at the points of intersection of the X and Y drivelines with the low-level signals are turned on sequentially. Once theindicating lamps are turned on, they may remains turned on even afterthe drive signals on the X and Y drive lines have returned to the highlevel. The above described graphic display device is ofa conventionaltype, for example disclosed in U.S. Pat. application Ser. No. 256,373,filed May 24, 1972 by Takashi lnoue. It is seen that the segmentconnecting the adjacent turned-on indicating lamps L indicates the inputdata on the line I, for example, the rate of change in response ratiowith respect to time.

FIG. 4 is a diagram showing a graphic display panel in which luminescentdiodes are used. In the embodiment of FIG. 4, an X driver circuit 8 iscomposed of transistors TR TR ,TR X driver lines X,, X X are connectedto the respective collectors of the transistors TR TR and in the samemanner Y driver lines Y,, Y Y, are connected to the respectivecollectors of transistors TR TR,,,,, which form a Y driver circuit 9.Luminescent diodes D,., D,,, are respectively connected to therespective crossing points on the X driver lines and Y driver lines X, XY, Y,,,. The respective emitters of the transistors TR,,, T ym composingthe Y driver circuit 9 are connected to a common power source +V, andcurrent controlling resistances R are connected to the Y driver lines Y,Y

For example, when X driver pulse P and Y driver pulse P have arrived,the transistor TR,., of X driver circuit 8 and the transistor TR of Ydriver circuit 9 are put on, and X driver lines X, and Y driver lines Y,are selected. As a result, current is passed through the luminescentdiode D,.,, and said diode luminesces. Next, when the driver pulse P,and P have arrived, X driver circuit L and L are selected, and the diodeD, luminesces. Thus, in the the same manner, the desired diodesluminesce in turn. Luminescent diodes do not remain on after theenergizing current is removed. Therefore, for statically indicating adesired curve on the display panel, it is necessary to repeat theabovestated action at a pre-set cycle in a conventional manner.

FIG. 5, which comprises 5A and 5B, is a blockdiagram of an embodiment ofthe invention in which produced when the display panel FIG. 4 is used.

In the block diagram of FIG. J, block 10 is a sampling pulse generatingcircuit as is explained in accordance with FIG. 2, and block 11 is thedisplay unit in which the luminescent diodes are used, as is explainedin accordance with FIG. 4. The indication surface 12 of the display unit11, is composed of 400 luminescent diodes (20 X 20) arranged in the formof matrix. For the sake of convenience, the explanation here is given onthe presumption that the abscissa (X-axis) X, X and the ordinate(Y-axis) Y, Y on the indication surface 12, are both designated by 5bits binary code. 15

is a recirculating type shift register of 100 bit structure storingbinary code signals of the ordinate (Y-axis) corresponding to each ofthe respective X,, X,, X signals in the direction of the abscissa(X-axis) on the indication surface 12.

Suppose that the Y-axis codes Y (j l, 2, 20) corresponding to positionX, are stored in the bit positions 99 to 95 of the register 15, and thatY-axis codes Y,- corresponding to X, position are stored on thefollowing bit positions 94 to 90 of the register 15, and in the samemanner Y-axis codes corresponding to X position are stored in bitpositions 4 to 0. Every time a clock pulse P, is given on the line 1,,the shift register 15 is read out serially by being shifted to the rightby one bit, and then the bit that has been shifted out is transferred tothe register 16 through the line 1 At the same time, the read out bit iscirculated through the line 1 AND Gate G OR Gate G and is re-stored intothe register 15. The register 16 is 5 bit shift register having thememory capacity sufficient for storing one Y-axis code. Therefore, whenthe first 5 pulses are given to the line 1,, an Y-axis code Y,corresponding to X, position is stored in the register 16. t

The counter 19 counts the clock pulse P, on the line 1,, and emits a 1signal per 5 counts. The above mentioned l. signal is supplied to theAND Gates G 4 G -5, through 1,. As a result, the gates 6 4 G -5 areenergized, and the content of the register 16 are parallelly read out.As is apparent from the above given description, when the first 5 clockpulses P, have arrived at the line 1,, the Y-axis code stored in theregister 16 corresponding to the X, position is parallelly read out, andthe is transferred to the buffer register 17 through the gates G ,-l G-5. Thereafter, the content of the buffer register 17 is decoded by Ydecoder 18, and one Y-drive signal P, corresponding to the abovementioned Y-axis code Y, is emitted.

The 1 signal emitted from the Counter 19 is supplied to Counter 20through the line I The counter 20 is 5 bit binary counter, and is astepped forward by the 1 signal emitted from the Counter 19. In otherwords, every time the shift register 15 is shifted to the right by 5bits, the Counter 20 is stepped by one count. As is apparent from theabove description, the Counter 20 designates the X positionscorresponding to the respective Y-axis codes stored the register 16. Thecontent of the counter 20 is decoded by an X-decoder 21.

When the first 5 clock pulses have arrived at the line 1,, the counter20 counts l and an X drive signal P for selecting X, position is emittedfrom the X-decoder 21. The X and Y driver circuits 8, 9 are driven bysaid Y-drive signal P, and said X-drive signal P,,, and the luminescentdiode on the coordinates (X,, Y,) luminesces. The operation of thedisplay unit ll was explained before in accordance with FIG. 3, and itis omitted here. Y-axis codes (Y,-, Y" are stored in the shift register16 every time 5 clock pulses P, arrive, and the X positions (X Xcorresponding to the respective Y-axis codes, are designated by Counter20. The contents of the shift register 16 and Counter 20 are decoded bythe decoders 18 and 21, respectively and a result, the luminescentdiodes on the coordinates (X,, Y',), (X Y",) are selected and luminesce.Thus, when a luminescent diode on the final position along the X-axis,i.e., on X the above mentioned operation is repeated. The content of theshift register 15 is visually indicated on the indication surface 12 inthe form of curve.

In this case, the indication surface 12 shows the student response to aquestion. The code signals designated the answer-rate are transmitted,after the 5 percent point, into the answer-rate register 13 through theinput line 1,. The answer-rate register 13 is 5 bit register as in thecase of the shift register 16. The l signal from the Counter 19 issupplied into the AND Gates G,-l G,-5 through the line I, and therefore,the content of the answer-rate register 13 is parallelly sent into theshift register 14 every time the five clock pulses P, have arrived, andthereafter, the content of the shift register 14 is serially read out onthe line I, by the clock pulse P, but Gate G is in its off state, andtherefore it is not sent to the register 15.

In this case, the 5 percent answer-rate corresponds to the graduation Y,of Y-axis, and the 10 percent answerrate correspondes to the graduationY In the same manner 100 percent correct answer rate corresponds to Yaxis. As explained in FIG. 2, when the time from the presentation of aquestion to the time when percent answer rate is obtained, is set to be(r), the repetitive cycle T, of the timing pulse P emitted from thetiming pulse generating circuit is represented by the formula givenbelow;

FORMULA:

In the above given formula n is presumed to be 5. And, the repetitivecycle of clock pulse P, is remarkably quick when compared with that ofthe timing pulse The timing pulse I emitted from the timing pulsegenerating circuit 10 is counted by Counter 22. The Counter 22 is a 5bit binary counter as in the case of the Counter 20. The comparatorcircuit 23 compares the countings of Counter 20 and Counter 22, and whenthe two countings coincide, l a signal is emitted to the line 1 AND GateG is put on ON state by 1 signal on the line 1 and AND Gate G becomes inthe OFF state. Here, N is an inverter circuit. Therefore, the answerratedata read out on the line 1 are written into the shift register throughthe AND Gate G and OR Gate 0,. Thus, the above mentioned operation isrepeated every time 1 signal is emitted onto the line 1 from thecomparator circuit 23, and the answer-rate data are written into theshift register 15. The content of the Counter indicates the respectivepositions X X on X-axis, and therefore, the data to be written into theshift register 15 correspond to the respective X positions. Thepositions X X X and X in the direction of X-axis correspond to 21', 31and 41-. Thus, the time graduations in X-axis are changed incorrespondence to the change of time 1-.

It should be understood that the system shown in FIG. 5 can be appliedto a display panel provided with discharge tubes.

FIG. 6, consisting of FIGS. 6A and 6B, is a diagram showing anotherembodiment in which a CRT is used. In FIG. 6, block 10 is a samplingpulse generating circuit, and 100 is an indicating CRT. In thisembodiment the indication surface of the CRT 100 is divided into a totalof 20 X 20 400 dots. A circulation type shift register 104 stores 400bits, and the respective bit posi tions correspond to the dot positionson the CRT 100. The content of the shift register 104 is supplied to theamplifier 105 by right hand serial shifting on the clock pulse P and atthe same time, the content of the shift register 104 is rewrittenthrough AND Gate G and an OR Gate G An amplifier 105 gives apredetermined brightness signal to the CRT 100 when a signal is giventhereto from the register 104.

A Y-Counter 106 is a 5-bit binary counter for counting the dot positionsin Y-axis (the perpendicular direction) while being supplied with clocksignal P,. The content of said Y-Counter 106 is converted into thecorresponding analogue voltage with D-A converter 107. The analoguevoltage of the converter 107 is amplified with the amplifier 108, and itis supplied to CRT 100 as the perpendicular deflection signal. In thesame manner, X-Counter 109 is a 5 bit binary counter stepped forward byone every time the Y-Counter I06 makes 20 counts. As is apparent fromthe above description, X-Counter 109 determines the respectivegraduation positions .of the electron beam on the X- axis. The contentof the X-Counter 109 is converted into the corresponding voltageanalogue by D-A converter 110, and then amplified with the amplifierIll, and is supplied as the horizontal deflection signal to the CRT 100.The above mentioned structure is the same as the structure of theconventional CRT display device, and therefore the explanations of thedetaiis of the conventional CRT display device are omitted here.

The indication data are supplied into the register 101 from the inputline 1, and are decoded by the decoder 102. The output line of thedecoder 102 is composed of 20 lines in correspondence to the number ofthe dot positions in the direction of Y-axis on the indication surface,and the 1 signal from the Counter 106 is supplied also to AND Gates G -lG -20. Therefore, every time 20 clock pulses P, have arrived, the outputof the decoder 102 is transferred parallelly to the shift register 103through the Gates G -l 6 -20. The content of the shift register 103 isserially read out on the line I by being right hand shifted under thecontrol of the clock pulse P The AND Gate 0;, is in the OFF statenormally, and therefore the data on the line 1 are not written in theshift register 104.

In the same manner as in FIG. 5, the timing signal emitted from theblock 10 is counted by Counter 112. The comparator circuit 113 comparesthe counting of Counters 109 and 112, and when the countings of the twocounters are the same, a l signal is emitted onto the line Thereby, ANDGate G is turned into OFF state, and AND Gate G is turned into ON state,and the 20 bit data on the line I are written into the shift register104 through the gates G and 6,. As can be easily understood, theposition of the data in the direction of X-axis written in said shiftregister 104, is designated by the counting of X-Counter 109.

The embodiments shown in the attached diagrams are mere examples, andvarious kinds of embodiments other than those given in the attacheddiagrams, can be thought of.

What is claimed is:

l. A graphic display system for indicating the dynamic answer responseof a set of answerers to a question comprising:

means for detecting the time lag between the posing of a question andthe response thereto by a defined subset of said answerers; means forproviding a timing signal having a cycle which is a defined function ofsaid time lag;

means for detecting the total number of responses to the question ateach of a plurality of sample times occurring at a frequency which is adefined function of the cycle of said timing signal; and

means for displaying the detected total number of responses for each ofsaid sample times on uniformly spaced consecutive portions of anindicating surface to provide a representation of a curve showing thedynamic answer response of the answerers to the question, wherein thespacing between said consecutive portions is a function of said timelag.

2. A graphic display system as in claim 1 wherein the displaying meanscomprise a two-dimensional indicating surface, an X-drive and a Y-driveeach indicating a position along one of said dimensions, means forproviding a display point at the intersection of the Y-axis indicated bythe Y-drive and the X-axis indicated by the X-drive, and wherein themeans for detecting the total number of responses at sample timesoccurring as a defined function of said timing signal comprise a currentresponse register for storing a count of the total number of answerresponses that have occurred, a timing signals counter for storing thecurrent count of the timing signals that have occurred, means fortransferring a decoded representation of the contents of the currentresponses counter to the Y-drive of the display means, and means fortransferring a decoded representation of the contents of the timingsignals counter to the X-drive of the display means, whereby the displaymeans displays a decoded representation of the total number of answerresponses at each occurrence of a timing signal, at an X-positiondefined by the current number of timing signals.

3. A graphic display system as in claim 2 wherein the display meansinclude a matrix of luminescent diodes.

4. A graphic display system as in claim 1 wherein the display meanscomprise a cathode ray tube and wherein the means for detecting thetotal number of answer responses at sample times occurring as a definedfunction of said timing signals comprise a register storing the totalcurrent count of answer responses, a

5. A graphic display system as in claim 1 wherein the display meanscomprise a matrix of gas discharge tubes.

6. A graphic display system as in claim 1 wherein the display meanscomprise a matrix of luminescent diodes.

7. A graphic display system as in claim 1 wherein the display meanscomprise a cathode ray tube.

1. A graphic display system for indicating the dynamic answer responseof a set of answerers to a question comprising: means for detecting thetime lag between the posing of a question and the response thereto by adefined subset of said answerers; means for providing a timing signalhaving a cycle which is a defined function of said time lag; means fordetecting the total number of responses to the question at each of aplurality of sample times occurring at a frequency which is a definedfunction of the cycle of said timing signal; and means for displayingthe detected total number of responses for each of said sample times onuniformly spaced consecutive portions of an indicating surface toprovide a representation of a curve showing the dynamic answer responseof the answerers to the question, wherein the spacing between saidconsecutive portions is a function of said time lag.
 2. A graphicdisplay system as in claim 1 wherein the displaying means comprise atwo-dimensional indicating surface, an X-drive and a Y-drive eachindicating a position along one of said dimensions, means for providinga display point at the intersection of the Y-axis indicated by theY-drive and the X-axis indicated by the X-drive, and wherein the meansfor detecting the total number of responses at sample times occurring asa defined function of said timing signal comprise a current responseregister for storing a count of the total number of answer responsesthat have occurred, a timing signals counter for storing the currentcount of the timing signals that have occurred, means for transferring adecoded representation of the contents of the current responses counterto the Y-drive of the display means, and means for transferring adecoded representation of the contents of the timing signals counter tothe X-drive of the display means, whereby the display means displays adecoded representation of the total number of answer responses at eachoccurrence of a timing signal, at an X-position defined by the currentnumber of timing signals.
 3. A graphic display system as in claim 2wherein the display means include a matrix of luminescent diodes.
 4. Agraphic display system as in claim 1 wherein the display means comprisea cathode ray tube and wherein the means for detecting the total numberof answer responses at sample times occurring as a defined function ofsaid timing signals comprise a register storing the total current countof answer responses, a counter storing the total number of timingsignals that have occurred, means for driving a first axis of thecathode ray tube as a function of the contents of said register, andmeans for driving a second axis of said cathode ray tube as a functionof the contents of said counter.
 5. A graphic display system as in claim1 wherein the display means comprise a matrix of gas discharge tubes. 6.A graphic display system as in claim 1 wherein the display meanscomprise a matrix of luminescent diodes.
 7. A graphic display system asin claim 1 wherein the display means comprise a cathode ray tube.